What is Verilog?

Verilog is a Hardware Description Language (HDL). What this means is that it is a textual language for describing electronic circuits and systems. When applied to electronic design, Verilog is intended to be used for:

• verification through simulation, 
• timing analysis, 
• test analysis (testability analysis and fault grading), and
• logic synthesis. 

For a more verbose description of Verilog visit the wiki page which has a good overview of the history.

The standard also defines the Programming Language Interface, or PLI. This is a collection of software routines which permit a bidirectional interface between Verilog and other languages (usually C).

Note that VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two different HDLs. They have more similarities than differences, however.

For some information regarding Verilog Design see the Doulos website: Verilog Designers Guide